Staff Hardware Design Engineer
Location: Krakow, Poland
Arteris connects innovation.
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
What You’ll Do as a Staff Hardware Design Engineer at Arteris
The role involves designing and developing advanced hardware components for ARTERIS IP products, ensuring their quality and timely delivery. As a senior engineer, you will be a key technical contributor in the development of highly configurable network-on-chip (NoC) solutions. You will work independently on complex problems and help guide technical best practices within the team.
Key Responsibilities
- Design and develop complex hardware blocks for configurable IPs, including advanced RTL coding and performance optimization.
- Actively participate in defining architecture specifications for NoC components and propose improvements.
- Develop sophisticated verification environments and define functional coverage strategies.
- Solve complex technical problems and provide technical support to other team members.
- Collaborate closely with hardware, software, and verification teams to ensure cohesive component integration.
- Contribute to the evolution of the team's design and verification methodologies.
- Actively participate in technical discussions with customers and the application engineering team.
- Document complex designs and mentor less experienced engineers on technical aspects.
What You Bring
- 8 to 12 years of experience in SoC/IP/NoC design
- Strong expertise in coherent and non-coherent communication protocols (AMBA, AXI, ACE, PCIe, CXL, CHI, or others)
- Excellent understanding of CPU architectures (ARM/RISC-V), cache systems, and memory coherence
- Deep experience with SoC/IP design flow (specification, architecture, RTL coding, verification, synthesis, DFT, timing and power constraints)
- Excellent complex problem-solving, communication, and team collaboration skills
- Advanced proficiency in Verilog/SystemVerilog and simulation/synthesis tools (Cadence/Synopsys/Mentor)
- Strong experience with SystemC, C++, Python, and scripting languages
- Ability to work independently and propose innovative solutions
- Fluent English (written and spoken)
Education Requirements
- Education: Master's degree (or equivalent) in electrical engineering, computer science, or related field
Estimated Base Salary
230 000 PLN to 270 000 PLN annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Arteris
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com.
With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.
