Reporting to the Manager of FPGA – Imaging, this Staff Engineer will lead the
delivery of best-in-class video processing solutions for our da Vinci systems (and
other robotic platforms), as part of an excellent cross-functional team. The
engineer in this position will work with the broader Vision and EE teams to
architect, implement and verify image sensor interfaces as well as novel solutions
for driving stereo and mono displays using FPGAs / FPGA SoCs deployed on the
platform.

The ideal candidate will possess a proven background in FPGA-based video
processing with deep expertise in image sensor interfaces and display driving
solutions – implementation and evaluation with the trade-offs between visual
quality, performance, and FPGA resource utilization in mind.

Responsibilities

Lead architecture of high-performance video processing pipelines and interfaces in FPGAs
Develop novel solutions for driving stereo and mono displays, optimizing for visual quality and system performance
Implement complex designs using (System) Verilog and verify in simulation and on hardware
Lead cross-functional collaboration to drive balanced trade-offs across resources, cost, performance, and practicality to deliver optimal video processing architectures
Mentor junior engineers and contribute to technical leadership within the FPGA team
Drive improvements to FPGA design and verification methodology; explore avenues to reduce development and verification time
Investigate and evaluate new FPGA / FPGA-SoC platforms for low-latency video processing
Provide technical guidance on FPGA architecture decisions and design reviews

Required Education, Skills & Experience

Minimum of 12 years of related experience and a Bachelor's degree; or 8 years experience and a Master’s degree; or a PhD with 5 years experience; or equivalent experience
Proven experience integrating image sensor and display interfaces
Extensive experience with video I/O standards and interfaces: HDMI, DisplayPort, MIPI CSI-2/DSI,GMSL, GigE, SDI; integration and customization of vendor/IP cores
Advanced proficiency with SystemVerilog, C (or C++) and scripting languages such as Python or TcL
Deep understanding of high-speed digital design, signal integrity, and associated challenges
Expert-level knowledge of FPGA build tools such as: AMD/Xilinx, Intel and/or Lattice
Strong foundation in FPGA simulation tools, environments and advanced test bench development
Expert understanding of static timing analysis / timing constraints and closure techniques
Experience leading FPGA part and pin selection process
Experience with Altera / AMD (Xilinx) / Lattice devices
Proficiency with revision control software (e.g., Git) and CI/CD workflows
Proven track record of technical leadership and mentoring
Strong communication skills and ability to influence cross-functional teams

Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19. Details can vary by role.

Intuitive is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.

We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits, and equity. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including experience, skills, and qualifications. The target salary ranges are listed.

Intuitive is an Equal Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

Mandatory Notices

U.S. Export Controls Disclaimer: In accordance with the U.S. Export Administration Regulations (15 CFR §743.13(b)), some roles at Intuitive Surgical may be subject to U.S. export controls for prospective employees who are nationals from countries currently on embargo or sanctions status.

Certain information you provide as part of the application will be used for purposes of determining whether Intuitive Surgical will need to (i) obtain an export license from the U.S. Government on your behalf (note: the government’s licensing process can take 3 to 6+ months) or (ii) implement a Technology Control Plan (“TCP”) (note: typically adds 2 weeks to the hiring process).

For any Intuitive role subject to export controls, final offers are contingent upon obtaining an approved export license and/or an executed TCP prior to the prospective employee’s start date, which may or may not be flexible, and within a timeframe that does not unreasonably impede the hiring need. If applicable, candidates will be notified and instructed on any requirements for these purposes.

We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.

Preference will be given to qualified candidates who do not reside, or plan to reside, in Alabama, Arkansas, Delaware, Florida, Indiana, Iowa, Louisiana, Maryland, Mississippi, Missouri, Oklahoma, Pennsylvania, South Carolina, or Tennessee.

Staff FPGA Engineer – Video

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