Staff Engineer, Packaging Engineering (Device Physical Failure Analysis)

We are seeking an experienced Device Physical Failure Analysis (PFA) Engineer with mandatory hands-on SEM and FIB expertise to support advanced semiconductor chip and package development. This role is part of the Chip Package Integration (CPI) Failure Analysis function and plays a key role in improving device reliability and influencing package and product design. The position interfaces closely with wafer fabrication (NAND and ASIC), package and product design teams, electrical and physical characterization, assembly R&D, and other process engineering groups.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Perform device-level physical failure analysis (PFA) using SEM and FIB techniques (mandatory).
• Conduct FIB cross-sectioning, delayering, and defect localization for root-cause analysis.
• Utilize SEM imaging to analyze device structures, interfaces, and failure mechanisms.
• Support chip structure optimization through detailed FA results and recommendations.
• Evaluate package reliability and robustness in response to fab process changes.
• Support package evaluation and qualification for NAND and ASIC technologies.
• Develop and maintain package recipe and process baselines based on FA findings.
• Identify and resolve structural and packaging-related reliability issues.
• Provide FA insights to influence package and product design decisions.
• Collaborate with fab process, package design, assembly R&D, and characterization teams.

REQUIRED:

• Bachelor’s degree or above in Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or related disciplines.
• More than 3 years hands-on SEM and FIB experience (MUST).
• Solid experience in physical failure analysis (PFA) of semiconductor devices.
• Strong understanding of device structures, packaging architectures, and failure mechanisms.
• Good English communication skills, both written and spoken.
• Ability to work effectively in cross-functional, global teams.

PREFERRED:

• Background in wafer fab processes and device design.
• Experience with NAND and/or ASIC technologies.
• Familiarity with electrical and physical characterization methods.
• Knowledge of assembly processes and advanced semiconductor packaging.
• Experience supporting fab or package process change qualification.

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