Silicon System Level Test Engineer

Job description As a Sr. SLT (System Level Test) engineer, this role will be responsible for building SLT  program to enable HVM shipment of our Silicon. Responsibilities

Test Development & Execution

- Develop SLT test programs, scripts, and automation for new products.

- Design and implement test hardware (board, socket, ATC) and fixture solutions for SLT platforms.

- Integrate system boards, peripherals, and interface cards for test setups.

Product Characterization

- Characterize device performance at system level across operating conditions and temperatures.

- Debug test failures to determine root cause—distinguishing between product, test setup, and software issues.

- Conduct ATE to SLT correlation to implement voltage guardbands.

Process & Quality Improvement

- Collaborate with DFT, validation, and product engineering teams to improve test coverage and efficiency.

- Optimize test time and throughput for high-volume manufacturing.

- Support yield analysis, test data correlation, and defect screening strategies.

Manufacturing Support

- Transfer SLT solutions from engineering to production.

- Train manufacturing test operators and technicians.

- Provide on-site and remote support to resolve production test issues.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred).

8-10 years of experience in semiconductor SLT, validation, or ATE test engineering.

Strong knowledge of system-level hardware architecture (CPU, memory, I/O, power).

Proficiency in scripting languages (Python, Perl, or similar) for test automation.

Hands-on experience with SLT platforms (e.g., HonTech / Chroma, Advantest Etc.).

Experience in debugging hardware/software interface issues.

Understanding of manufacturing test flows and yield analysis.

Education and Experience

Bachelor’s or Master’s Degree in technical subject area.