Senior Verification Engineer (FPGA)

At D-Fend Solutions, our people are our greatest strength — and technology is our passion. Our team of innovators and subject matter experts, including veterans of elite military intelligence technology units, is transforming the way organizations protect themselves from drone threats. As the global leader in cyber-takeover counter-drone technology, we design and deliver advanced, software-defined solutions that empower our customers to detect, take control, and safely land unauthorized drones — with precision and reliability. Every day, we push the boundaries of innovation to meet real-world security challenges across industries and environments. We’re proud of our cutting-edge technology, our global reach, and the impact we make in securing the skies. We’re seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment — those who want to be part of the next generation of airspace security innovation. Join D-Fend Solutions and help make the world a safer place. Become a D-Fender! Work with the world’s leading cyber-takeover counter-drone technology provider and shape the future of safe airspace. Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments. You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.     Key Responsibilities:

Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.

Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.

CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).

Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.

Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.

Minimum Qualifications:

7+ years of professional functional verification experience for FPGA or ASIC designs.

At least 5 years of proven expertise in building a complete Full-Chip UVM test environment from scratch.

Strong command of SystemVerilog and Verilog.

Extensive experience with EDA tools (specifically Questa) and complex hardware debugging.

FPGA Knowledge: Prior experience or background with FPGAs is a significant advantage.

 

Preferred Qualifications:

Proficiency in Matlab for DPI or bit-exact modeling.

Scripting experience (Python/Tcl/Bash) for building automated CI/CD regression flows.

Familiarity with Questa tools is preferred.