Principal Engineer, VLSI Design Engineering (SOC Verification, System Verilog, UVM)

Job responsibilities:  

• 8+ Years of relevant Logic Verification experience 

• Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC 

• Create verification environment using UVM methodology 

• Create reusable bus functional models, monitors, checkers and scoreboards 

• Drive functional coverage driven verification closure. 

• Work with architects, designers, and post-silicon teams 

• Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions 

• Development of tools for Design and Verification support 

• Debug failures and root-cause it by interacting with other teams/groups Etc. 

• Skills Required/Preferred: 

  - Software Skills Required: 

• Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis 

• Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable  

•  

  - Functional Verification: 

• Unit/Sub-system/SOC level verification experience 

• Experience in leading verification closure of complex IP/SOC for at least one project 

• Exposure to industry standard verification tools for simulation and debug 

• RTL & Gate Level Simulations 

• Proficiency in Verilog, System Verilog & Assertions , UVM and Functional Coverage 

• Exposure to Verification Fundamentals  

• Verification Automation using scripts  like Perl,shell,tcl/tk 

• Good debugging and problem solving skills. 

• Good communication skills and ability, desire to work as a team player   

• Exposure to Analog verification will additional plus point 

•  

  -Digital design Concepts 

                  -  CMOS VLSI, Digital Circuits 

                  -  Knowledge on Memory (preferred) 

                    (SRAM/DRAM/ROM/Flash) Circuits/Logic 

               - Preferred exposure  

                                  - NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal 

                                  - Cadence Schematic and layout environment 

   





 
•  
•  

• Education: 

• B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.