Rivos Power Design team is seeking highly motivated candidates to perform post-silicon power activities for the new high performance power efficient SOC designs.The primary role is to engage in power hardware validation and analysis of typical workloads on server compute silicon.
Responsibilities
As a Post-Silicon Power Engineer, you will own or participate in the following:
Analyze workloads and their power dissipation to drive the power optimization to achieve best-in-class power/performance ratio
Measure silicon power dissipation of typical server workloads (data analytics, graph algorithms, and AI/ML), analyze data, and correlate measurements with simulation results
Collaborate cross-functionally with design, architecture, systems, and software teams to enable enterprise customer use-case power measurements
Perform silicon power measurements and correlate with partition simulations and full-chip projections
Improve use-case power/perf ratio through tuning of hardware and software settings
Silicon register tuning to achieve power and thermal stability
Automate power measurement infrastructure
System level power & performance debug.
Requirements
Applicants with strong programming skills and understanding of low-power digital design and power fundamentals, including:
Skilled in Assembly, C, Python, and shell programming plus associated tool chains
Use of lab equipment such as multi-meter units, oscilloscopes, etc
CMOS dynamic and static power calculation
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
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