Lead FPGA Architect

Lead FPGA Architect

About Niobium

Niobium Microsystems is unlocking the full potential of sensitive data without compromising privacy.

We believe organizations shouldn't have to choose between data security and data utility. The Niobium Encrypted Cloud is a high-performance Infrastructure-as-a-Service (IaaS) platform designed to make encrypted computation easier, faster, and practical for real-world applications. By leveraging our custom accelerators within a cloud environment, we enable customers to process their most proprietary information while it remains fully encrypted. With Niobium, data is never decrypted, never exposed, and never vulnerable—allowing you to compute with confidence.

Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, Niobium’s team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.

About This Role

We are seeking an FPGA expert to serve as the lead for our FPGA development efforts. You will be the primary architect and lead developer responsible for optimizing our proprietary FHE algorithms for the AMD Alveo V80 platform. This is a high-impact role where you will do hands-on FPGA development with support from our talented ASIC team. Niobium customers will use the FPGA on Niobium’s Encrypted Cloud for developing FHE applications.

Your mission is to turn our "mathematically guaranteed privacy" vision into a high-performance reality. You will act as the technical lead for our FPGA, eventually growing and leading a team as we scale our hardware infrastructure. Niobium customers will use the v80 implementation as a temporary stand-in for our custom ASIC, The FPGA is also a parallel development path for our next-generation hardware.

Responsibilities

FPGA Architecture & RTL Development:

• Lead the Porting Effort: Take Ownership of porting our existing ASIC RTL to the AMD Alveo V80. Ensure the design is scalable, parameterizable, and optimized for the Versal HBM architecture. 
  
• Parallel Path Strategy: Architect the RTL to support a unified codebase for both FPGA and ASIC targets. Implement abstractions for memory, clocking, and resets that allow for seamless migration between programmable logic and custom silicon
• Performance Engineering: Optimize the CKKS FHE data pat, including: NTT, KeySwitching, and Base Conversation to exceed the performance of state-of-the-art GPU implementations.  
• Subsequent Version Testing: Use the FPGA platform as an iterative testbed to validate code and architectural improvements for future generations of our hardware. 

Toolchain:

• Debug Guru: Resolve the current team's challenges with debugging and toolchain experience. Implement robust hardware debugging strategies using Vivado Hardware Manager, ILA cores, and Vitis emulation flows.
• Timing Closer & Optimization: Take full responsibility for achieving timing closure on high density Versal designs. Optimize the design for resource utilization (LUTs, DSPs, URAM) and power efficiency).
• NoC Configuration: Architect and tune the Versal Programmable Network-on-Chip (NoC) to prioritize high bandwidth data movement between HBM2e and the PL fabric. 
  

Leadership & Scaling:

• Building the Team: Initially lead backend and frontend engineering efforts, then assist in hiring and technical leadership of a multi-disciplinary team (Backend, Frontend, DevOps, Customer Support) to support growth from 5 pilot users to thousands of concurrent users. 
• Security & Compliance: Ensure the infrastructure meets enterprise-grade standards from day one, preparing the platform for HIPAA, SOC2, and GDPR compliance. 

Required Technical Expertise

• Senior FPGA Architect: 10+ years of experience in FPGA design and development, with at least 5 years specifically in high-performance computing (HPC) or hardware acceleration.   
• AMD Versal / Alveo Expert: Deep experience with the AMD Vivado/Vitis toolchain and the Alveo Versal Example Design (AVED). You have successfully deployed designs on Versal or UltraScale+ HBM platforms.   
• RTL Craftsmanship: Mastery of SystemVerilog or Verilog for complex SoC design. You understand the nuances of RTL for both FPGA and ASIC and can write portable, high-quality code.   
• Mathematical Hardware Design: Experience implementing complex arithmetic algorithms (e.g., FFT, NTT, modular arithmetic) in hardware. Familiarity with fixed-point arithmetic and high-precision calculations is essential.   
• Protocol Proficiency: Strong knowledge of high-speed interfaces, including PCIe Gen4/Gen5, AXI4, and HBM2e.

Location

Niobium is headquartered in Columbus, Ohio. Employees are primarily located coast to coast across the U.S. and other countries. This role is a remote position.

Benefits

Niobium offers a highly competitive benefits program to support employees and their families, including:

• Competitive salaries 
• Equity in the form of Incentive Stock Options (ISO)
• Employer paid medical insurance plan
• Health Savings Account (HSA) with employer contributions
• Dental and vision reimbursement account (HRA)
• 401(k) retirement plan with employer match
• Flexible work location with remote options
• Flexible time off