Role: Hardware Design Intern

Type: Full-time paid internship

Duration: at least 8 weeks, starting June/July 2025

Team: Design Team, Brno Design Center

Location: Brno, Czech Republic (on-site)

Codasip develops a portfolio of RISC-V based processors, easily customizable using a unique toolset, Codasip Studio. As a Hardware Design Intern, you will be assigned to a design team developing our next generation of RISC-V processor cores, or performing customisation work for an existing core. The work will be meaningful and project related, using the latest EDA tools for silicon design. Work could be on architecture, design and verification activities and we are looking for enthusiastic people with a willingness to learn and contribute. You will be assigned a mentor who will guide you through your placement and help you develop your skills beyond those which can be learned in a lecture theatre environment.

Requirements

Preferred Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of modern CPU architectures (ideally RISC-V) and microarchitectures.
• Familiarity with hardware description languages such as VHDL, Verilog, or SystemVerilog (academic or project experience is a plus).
• Interest in digital design synthesis and implementation flows.
• Basic knowledge of version control tools like Git.
• Introductory experience with Linux.
• Strong communication skills in English.
• Enthusiasm for learning and a proactive attitude toward self-education in hardware design.

Benefits

What is Codasip about?

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

Our processor cores are based on the RISC-V open architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.

Codasip is a private company backed by well-funded EU grants. Our products are already making a real impact, with billions of devices already in the market powered by our processor IP and tools.

Some useful links on Codasip:

• Codasip RISC V Processor Solutions
• Velký technologický úspěch. Česko povede vývoj evropského počítačového procesoru
• Design for differentiation: architecture licenses in RISC‑V
• Building a Swiss cheese model approach for processor verification
• www.zvut.cz
• Efficient verification of RISC-V processors – Technical paper
• Přednášky FIT VUT