Emulation Manager

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Emulation Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the emulation strategy for chips that power the world's largest AI clusters.

As an Emulation Manager, you will be a foundational member of our Israel R&D center, leading the emulation testing efforts that ensure our silicon meets extreme quality and performance targets required for AI scale. You won't just execute tasks—you will build a world-class emulation team from scratch, owning the end-to-end vision from high-level model generation to complex system-level testing and silicon-accurate debugging. You will be the bridge between hardware and software teams, ensuring our connectivity solutions are rigorously validated before tapeout and enabling rapid time-to-market for critical AI infrastructure silicon.

Key Responsibilities

• Build a world-class Emulation team from the ground up. You will own the end-to-end vision—from high-level model generation to complex system-level testing and silicon-accurate debugging 
• Lead the selection and integration of next-generation emulation platforms. You will partner directly with top-tier EDA vendors to co-develop cutting-edge methodologies that push the boundaries of what emulators can achieve 
• Orchestrate comprehensive testing plans with FW, SW, and Validation teams. You will be the bridge that ensures our hardware-software integration meets the extreme performance and quality bars required for AI infrastructure 
• Take a hands-on lead in the high-stakes environment of initial model bring-up. You will solve the "impossible" bugs, ensuring rapid cycles from RTL to functional verification 
• Continuously evolve emulation flows to reduce compile times and increase execution speed, directly accelerating our time-to-market for critical AI silicon 

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering 
• 10+ years of hands-on experience in Emulation at leading semiconductor companies 
• Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills 
• Deep expertise in Emulation flows for Large chips, working on Industry standard emulators Zebu, Palladium or Veloce, Verification or Design experience working with system Verilog for develop, testing and debug complex chips, 
• Developed execution flows for building, running and debugging emulation models  
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration 

Preferred Qualifications

• Familiarity with EDA tools for Lint, Clock domain crossing, simulation, debugging, synthesis and timing analysis 
• Knowledge in scripting languages such as Python