DFT Engineer

DFT Engineer (Senior / Staff)

At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner for DoD and commercial customers whose solutions require lower power, higher efficiency, and proven security.

Founded as a 2021 spinout from a world-class security and computing systems R&D company, our team combines decades of experience in advanced semiconductor design with experience in advanced cryptography. Niobium is headquartered in Dayton, Ohio with additional locations in Portland, Oregon; and Columbus, Ohio. We will not be limited by geography for the right candidate.

POSITION DESCRIPTION /

Niobium Microsystems is seeking a Senior / Staff DFT Engineer with 8+ years of relevant industry experience. This role will serve as a technical lead responsible for defining and executing Design-for-Test (DFT) strategy across complex SoC designs.

As a DFT Engineer, you will own the full test insertion flow from early architecture through post-silicon validation. You will collaborate closely with RTL, physical design, and test engineering teams to ensure high fault coverage, manufacturability, and first-pass silicon success.

JOB RESPONSIBILITIES /

Primary Responsibilities:

• Overview
  • Own and drive end-to-end DFT strategy for complex SoCs, from architecture through silicon bring-up
  • Serve as DFT lead for major subsystems or full-chip execution
• DFT Architecture & Planning
  • Define and implement DFT architecture including scan, compression, and MBIS
  • Establish DFT insertion strategies at RTL and/or netlist stages
• Implementation & Integration
  • Drive scan chain stitching, compression insertion, and clock/reset domain handling
  • Integrate DFT features across subsystems including SRAM, register files, and mixed-signal blocks
  • Collaborate with physical design to meet timing, routing, and signoff requirements
• Verification & Coverage Closure
  • Execute ATPG and fault simulation to achieve high fault coverage targets
  • Develop and validate test patterns for scan, BIST, and low-power modes
  • Track and drive DFT sign off criteria including coverage, waivers, and escape analysis
• ATE & Post-Silicon Bring-Up
  • Partner with test engineering to translate patterns to ATE platforms
  • Support silicon bring-up, debug failing patterns, and perform yield analysis
  • Conduct shmoo analysis and root-cause failures
• Leadership & Methodology
  • Drive DFT methodology improvements, automation, and flow optimization
  • Develop scripts and infrastructure for scalable DFT flows
  • Represent DFT in cross-functional reviews and program milestones

DESIRED SKILLS & EXPERIENCE /

• Required Experience
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of hands-on DFT experience in ASIC or SoC design
  • Strong expertise in scan architecture, ATPG, compression techniques, and MBIST
  • Experience driving DFT from RTL through GDSII, including physical design collaboration
  • Hands-on experience with ATE bring-up and post-silicon debug
  • Proficiency in scripting (Tcl, Python) for automation and flow development
• Technical Experience
  • DFT tools such as Siemens Tessent, Synopsys TestMAX, or equivalent
  • Familiarity with RTL design and simulation tools (Verilog/SystemVerilog, VCS, Xcelium)
  • Experience with large-scale SoC integration and multi-clock/multi-power domains
  • Strong understanding of DFT timing, physical constraints, and signoff requirements
  • Experience working with ATE platforms such as Advantest or Teradyne is a plus

BENEFITS /

• Competitive salaries 
• Employer paid health care
• Employer contribution to health savings account
• Flexible time off
• Flexible work location with remote options
  • Location Preferences: Portland, OR;Columbus, OH; Dayton, OH; Fayetteville, AR; or San Francisco, CA
• 401K employer match

CONTACT /

[email protected]

444 E 2nd Street, Suite 250, Dayton, OH 45402

niobiummicrosystems.com