Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About the role

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Design Verification Manager, you will lead the quality and reliability strategy for our Israel R&D center. You will be responsible for steering the verification roadmap, overseeing the development of complex testbenches, and ensuring our next-generation AI silicon meets the highest standards of excellence. Leading a team of talented engineers, you will tackle challenges at the unit, sub-system, and full-chip levels, playing a pivotal leadership role in delivering high-performance hardware for the world’s largest AI clusters.

Key Responsibilities

Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital designs
Oversee the architecture and maintenance of multiple verification strategies including DV using SV-UVM, Formal and Emulation
Define functional coverage goals and quality metrics, driving the team toward 100% verification closure and sign-off
Partner closely with Design, Architecture, and Backend teams to align on specifications, root-cause complex bugs, and optimize the hardware development cycle

Basic Qualifications

B.Sc. in Electrical Engineering from a leading academic institution
15+ years of proven experience in ASIC verification, with at least 5+ years in a technical leadership or people management role
Deep hands-on expertise in architecting complex small (IPs,Blocks) and large (full chip,SoC) verification environments
Expert-level knowledge of verification methodologies
Proven ability to manage project timelines, resource allocation, and the professional growth of team members
Exceptional interpersonal skills with the ability to navigate a fast-paced, collaborative R&D environment and influence stakeholders

Preferred Qualifications

Experience of SV-UVM verification of complex sysems
Experience implementing Formal Verification or Emulation strategies at a team level
Proficiency in Python/Tcl for environment automation and a track record of improving verification productivity
Deep understanding of high-speed industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Design Verification Group Manager

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