Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary ASIC Physical Design Group manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As the ASIC Physical Design Group manager, you will be a Key member of our Israel R&D center. You will build the physical implementation team for chips that drive the world’s largest AI clusters. You will lead the team and the transition from RTL to GDS, ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

Build and mentor a high-performing Back-End group, owning the end-to-end flow from Synthesis to Signoff
Establish cutting-edge RTL-to-GDS flows and physical design methodologies tailored for advanced process nodes
Take full ownership of physical implementation, including floorplanning, P&R, CTS, Power/Clock distribution, Power integrity and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power Performance Area (PPA). This involves conducting feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Lead and guide external contractors and global partners to ensure seamless execution and delivery
Address complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon

Basic Qualifications

B.Sc. or M.Sc. in Electrical Engineering
15+ years of hands-on experience in Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
Proven experience in leading teams or projects with a "can-do" approach and excellent communication skills
Deep expertise in RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs
Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
Experience managing both complex Macro-level designs subsystem level and Full-Chip integration

Preferred Qualifications

Deep understanding of Power & Noise analysis (EM/IR)
Experience with DFT (Design for Test) integration
Background in high-speed interfaces or data center protocols

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

ASIC Physical Design Group Manager

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