SEAKR is seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics.
- The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test.
- The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements.
- Ability to architect and construct full test environments for simple devices using UVM, including coverage, is required.
- The candidate shall be capable of diagnosing sophisticated test failures and filing results
- Ability to analyze Verilog RTL to diagnose test failures is required.
- Ability to perform and evaluate regression tests for a design under test is a plus.
- Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required.
- Must be able to work effectively under pressure to meet tight deadlines.
- A Bachelors degree in Electrical Engineering or Computer Science is required, a Master's Degree is preferred.
- At least 7 years of verification engineering experience are required.
Compensation: Base pay range is $100,000-$135,000 depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligibl20for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA.
SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines.
US Citizenship Required
