Rivos Power Design team is seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for the new high performance power efficient SOC designs. The role will be at the center of a state-of-the-art power design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.
Qualifications
- We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition.
- Familiar with power intent definition, implementation and verification flows.
- Familiar with entire RTL2GDS flow (RTL sim , equivalence, synthesis, P&R, intent checking)Drive coverage of power intent across static and dynamic checking methodologies.
- Understand interactions of the product at the software and system level that impact power.
Requirements
- Bring up power intent checking flows on new projects.
- Knowledge of scripting languages like, Tcl and Python.Interface with CAD and physical design verification team for debugging any power intent flow issues.
- Work with RTL and DV team on debugging issues related to power aware simulations.
- Knowledge of various implementation and architectural techniques for low power optimization.
- Strong communication and interpersonal skills are required along with the work in a dynamic, global team.Excellent scripting skills Tcl and Python.
Education and Experience
- Minimum industry experience of 5+ years.
- PhD or Master’s Degree in EE, EECS or CS.
