Experience Level 13 – 17 years
You should have strong knowledge and experience with all aspects of the SOC Architecture, Design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers. You should be highly motivated with strong communication skills, attention to detail, and quality oriented. Candidates with a take-ownership attitude will succeed in this role.
Responsibilities include, but not limited to:
- Reviewing product and FW requirements
- Working with other ASIC architects and with system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs
- Defining requirements for ASIC design, verification, and physical implementation teams
- Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
- Reviewing and configuring 3rd party IPs
- Supporting other teams in the ASIC organization and reviewing their work
- Supporting product teams with documentation, code-reviews, and silicon debug
- Continuously finding opportunities for improving design quality and design practices
- Drive Architectural innovation and file patents and trade secrets
Preferred Skills:
- Experience with HW modeling languages
- ASIC architecture experience in NAND based storage products (e.g. SSD, eMMC, USB drive, SD Card)
- Design/architecture experience with high-speed serial and parallel interfaces (e.g. PCIe, SD, USB, UFS)
- Work experience on high speed memory Interfaces like DDR, NAND Flash
- Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering
- 10+ years of ASIC Design/Architecture experience with knowledge of USB, SD, PCIe + NVMe or UFS in a storage application
- RTL design experience in Verilog/SystemVerilog
- Knowledge and experience in various aspects of SOC design, verification, and implementation flows
- Experience with low-power design techniques
- Ability to read and understand SW code
- Understanding of CPU and memory architectures, datapath pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies
- Excellent Logic design and debug skills; proficiency in protocols like USB/SD/PCIe; knowledgeable in bus protocols like AHB/AXI/I2C/UART/JTAG/CJTAG
- Should work with Verification, FW, Validation, Analog, IO, Physical Design, ATE test, Chaz and Quality teams to architect, design and debug
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