As part of the ASIC modeling team, the candidate will work on developing, maintaining and testing the NAND/SoC models using C/C++/SystemC. The SoC models capture the register accurate functionality of the controller chip which manages the NAND storage.
Experience:
4 to 7 years
Must have:
Experience in DFT implementation, Verification
Experience in MBIST implementation, Verification
Strong DFT/MBIST fundamentals
DRC Clean up | Coverage improvement | Understanding and modifying MBIST algorithms
Pattern validation flows | Zero/Unit delay | SDF based
Good to have:
PERL/TCL Scripting /Python
Usage of assertions for monitoring clock frequencies and other test related registers
Yield analysis and improvement flow
Understand CLP constructs and can work in multi-voltage, multi-power design
Expected Roles:
Need to architect DFT based on the PETE, Design and Customer specifications
Should be self motivated, self driven and eager to learn
Qualifications
BE/Btech//Mtech/ME
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