Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Minimum Qualifications:
Minimum of 15 years of experience in ASIC/SoC design and/or verification environment
Very strong debugging and problem-solving skills supported by relevant experience
Digital logic design and implementation in advanced technology nodes
Working experience in UVM environment
Languages: C, C++, Python, Java, Verilog (or VHDL), SystemVerilog
Preferred Qualifications:
Leadership skills
Familiarity with formal verification methods
Familiarity with standard ASIC/SoC design flows including synthesis, DFT, STA, UPF, and ECO flows
Experience in low-power design techniques
Working knowledge of NVMe, PCIe, DDR and ARM standards
Familiarity with big box emulation platforms
Proven ability to architect and lead IP/SoC-level verification efforts
Salary Range: $177,450 - $266,150
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