SoC Architect, Microarchitecture and Modeling

Lab Overview:

The Samsung SOC Lab vision provides innovative SoC architecture, bus / memory subsystem, Multimedia blocks (ISP, Display, Media encoder/decoder), CPU, GPU , AI/ML IP definition for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung's strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

Position Summary:

We are looking for a Lead SOC Architect to lead development of Power manager, Sensor Hub and Audio subsystem architecture in next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to Power manager, Sensor Hub and Audio sub-system architecture, interface, performance, and power tradeoffs.

Position Responsibilities:

• Develop high level micro-architecture of Power manager, Sensor Hub and Audio IPs in collaboration with SoC Arch
• Perform high-level performance modeling/simulation and analysis of Power manager, Sensor Hub and Audio features, applications, benchmarks, and complex use cases
• Workload characterization of Power manager, Sensor Hub and Audio IPs in a laboratory setup
• Guide on development of innovative Power manager, Sensor Hub and Audio Architectural and microarchitectural features to boost PPA (Performance, Power and Area) on various targeted workloads in next generation SOCs
• Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across organization (SW, HW, Architecture, Leadership)
• Collaborate with SoC modeling team to evaluate architectural proposals for Power manager, Sensor Hub and Audio IPs
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations

Required Skills:

• BSc, Masters or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 10+ years of experience in SOC or ASIC RTL design and architecture
• Prior direct experience (> 7 years) in Power manager, Sensor Hub and Audio architecture or microarchitecture is required
• High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around Media, Display and Audio
• Ability to leverage existing simulation capabilities [GEM5, FastSIM, Platform Architect] or create new simulation capabilities when necessary
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), existing and emerging Media, computer vision and Audio standards
• Leadership across hardware, software, and platform groups to align all parties to a common vision