Rivos is hiring a

Silicon CAD Front End- Full time

Bengaluru, India
Full-Time
Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a CAD Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
As a CAD Engineer focusing on the methodology and support of RTL design, you will work with architecture, design, software and verification leads to develop technology critical to the development of our products. You will be involved from conception to final creation and every step along the way.

Responsibilities

  • Work with chip leads to understand the logic design and verification methodology and high level requirements in support of RTL design
  • Collaborate with chip leads to determine other areas to support current or future designs that can benefit from automation and tooling
  • Define and implement new infrastructure capabilities, tool flows, and environments that can be used to accelerate design and development

Requirements

  • Strong fundamentals in digital ASIC design; experience using SystemVerilog
  • Strong skills in various front end design tools and techniques such as logic equivalence, lint checks, clock and reset domain crossing and DFT
  • Knowledge of SOC/CPU architecture
  • Familiarity with high performance and low power design techniques
  • Hands on experience in digital design
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
  • Ability to work well in a team and be productive under aggressive schedules.
  • 3-6 yrs of experience

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

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