Experience Level 10 – 20 years
You should have strong knowledge and experience with all aspects of the SOC design and implementation flow – including datapath design, low power design, clock and reset schemes, coverage driven verification, synthesis, P&R, STA, DFT, power-islands, floor-planning, CTS, IR-drop – and an understanding of how architecture decisions impact these flows. You will be responsible for developing, contributing, and leading ASIC macro and micro-architecture activities in our storage-based controllers. You should be highly motivated with strong communication skills, attention to detail, and quality oriented. Candidates with a take-ownership attitude will succeed in this role.
Responsibilities include, but not limited to:
- Reviewing product and FW requirements
- Working with other ASIC architects and with system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs
- Defining requirements for ASIC design, verification, and physical implementation teams
- Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions
- Reviewing and configuring 3rd party IPs
- Supporting other teams in the ASIC organization and reviewing their work
- Supporting product teams with documentation, code-reviews, and silicon debug
- Continuously finding opportunities for improving design quality and design practices
- Drive Architectural innovation and file patents and trade secrets
Minimum Qualifications:
- Bachelor/ Master degree in Electronics/VLSI/Micro-Electronics Engineering
- 10+ years of ASIC Design/Architecture experience with strong knowledge of USB, SD, PCIe + NVMe and/or UFS in a storage application
- RTL design experience in Verilog/SystemVerilog
- Knowledge and experience in various aspects of SOC design, verification, and implementation flows
- Experience with low-power design techniques
- Ability to read and understand SW code
- Understanding of CPU and memory architectures, datapath pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies
- Excellent Logic design and debug skills; proficiency in protocols like SATA/USB/PCIe; knowledgeable in bus protocols like AHB/AXI/I2C/UART/JTAG/CJTAG
- Should work with Verification, FW, Validation, Analog, IO, Physical Design, ATE test, Chaz and Quality teams to architect, design and debug
Preferred Skills:
- Experience with HW modeling languages
- ASIC architecture experience in NAND based storage products (e.g. SSD, eMMC, USB drive, SD Card)
- Design/architecture experience with high-speed serial and parallel interfaces (e.g. PCIe, SATA, SD, USB, UFS)
- Work experience on high speed memory Interfaces like DDR, NAND Flash
Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
