Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
We are looking for Senior Principal Design Verification Engineers with proven experience in working on industry-standard protocols such as DDR or CXL/PCIe. Using your coding and protocol expertise, you will contribute to the functional verification of the designs from coming up with block-level and system-level verification plans to writing test sequences, test execution, collecting and closing coverage.
Basic qualifications
Required Experience
Preferred Experience
The base salary range is USD 184,000.00 – USD 270,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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