As a logic design and/or verification engineer, you will play a central role in ensuring performance of 3D NAND designs. Your expertise will be crucial in designing and verifying NAND design that meet its stringent power, performance specs and driving development of world class verification strategies to guarantee worldclass reliable products.
Key Responsibilities
- Design logic and develop microcode to enable features to improve performance.
- Perform logic verifications of 3D NAND designs using latest methodologies.
- Generate verification and coverage plans, construct necessary ULT test benches and fullchip models to achieve comprehensive coverage.
- Troubleshoot and resolve logic and microcode bugs within pre-si verification and post Si validation.
- Collaborate with architects, analog and Core designers and APR teams to enhance and achieve power, performance and functional targets. Formulate functional and Dfx test plans that are comprehensive including system centric validation tests.
- A Master's degree in Electrical or Computer Engineering with at least 5 years of relevant NAND experience, or a bachelor's degree in Electrical or Computer Engineering with 7+ years of relevant experience.
- Proficiency in Verilog, System verilog and industry standard logic simulation tools is a must.
- Expertise in test bench development using system verilog and UVM/OVM concepts. Experience in test generation, SVA, coverage analysis, failure debugging is a must.
- Automating using Perl, Python,C/C++ or TCL is a plus.
- Prior experience in 3D NAND memory design will be considered a significant asset.
For California, Colorado, New York, Washington, and remote roles: The compensation range for this role is $127,260 - $203,620. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.
