- DPPM (Defective part per million) owner of all NAND products in WDC. Drive NAND development from pre-silicon (circuit simulation for stress/screen test method), 1st silicon to qualification. Develop and define test strategy and test flow for miscellaneous NAND silicon based on DOEs result from dedicated R&D platform.
- Performing deep electrical failure analysis during new product development and ramping phase. Shoot failures from both wafer level and package level. Create analysis report based on FA finding and define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.)
- Monitor memory health level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction.
- Define the test flow, screen/stress method based on root cause analysis of failures. Work with TE to come up with detail plans and drive for implementation.
- BS or higher in Electrical Engineering, Computer Engineering, Physics, Materials Science or other related technical field
- Deep understanding on electrical failure analysis methodology.
- Demonstrated ability to analyze problems, diagnose root cause, and apply corrective actions.
- Excellent data analysis skills including data crunch, statistical analysis, and interpretation
- Highly self-motivated, passionate about troubleshooting and solving complex problems
- A basic understanding of system, F/W working principle, device physics is beneficial
- Good English communication skill
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