Senior Engineer, ASIC Development Engineering

1. Development of ASIC verification and Validation plans
2. Development of C/UVM tests for ASIC verification and validation to achieve comprehensive coverage
3. Working with ASIC design and architecture teams to understand functionality of logic blocks of SSD controller
4. Comprehending ＂big picture＂ at the ASIC architectural and system level as well as executing at the detail block level.

1. Master/Bachelor's degree in Electrical Engineering or Computer Science.
2. Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred.
3. Knowledge of ARM AMBA Bus protocols
4. Knowledge of C and SystemVerilog.
5. Knowledge of UVM verification methodology
6. Experience in C code development for System validation.
7. Familiar with scripting language like Perl/Python/Tcl

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