Bachelors or Masters in Electronics/Electrical Engineering
- Minimum 3+yrs of experience in ASIC/IP Digital Design for large SOCs
- Expertise in implementation of RTL in Verilog/SV for complex designs with multiple clock domains
- Expertise with various bus matrices on AHB, AXI and NOC designs
- Working knowledge of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
- Experience in ARM processor and/or NAND Flash subsystems would be a plus
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks, report analysis and signoff
- Experience in Synthesis using DC, timing analysis and closure would be a plus
- Experience of UPF flow, defining constraints working with PD teams
- Expertise in Perl, Python, TCL language is a plus
- Ability to ramp-up quickly and work cohesively with Verification/Validation teams
- Must have a good attitude and be solution-oriented
- Excellent written and verbal communication skills
- Bachelors 3+ yrs experience or Master 3+ yrs experience or PhD with 3+ yrs experience in CS, CE, EE, EC or equivalent required.
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