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Astera Labs is hiring a

Senior Advanced Design Verification Engineer

Santa Clara, United States

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

Job Description:  

As the Advanced Design Verification Engineer, you will lead next-generation ASIC infrastructure initiatives, including the development of tools and infrastructure targeting efficiency and reuse spanning DV, Emulation, pre, and post-silicon.  

Basic Qualifications:  

  • Strong Academic and technical background in computer / electrical engineering. MS in EE or Computer Engineering is preferred.  
  • 5+ Years of related experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.   
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.  
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 
  • Authorized to work in the US and start immediately. 

Required Qualifications:  

  • Experience in ASIC Emulation and/or Design Verification.  
  • Experience with simulation and emulation platforms with domain expertise in high-speed protocols. 
  • Experience working with PLI/DPI and other emulation interfaces.  
  • Experience in programming and scripting languages (like Perl/python/C/C++).
  • Experience in a role requiring interaction with senior leadership (e.g., Director level and above).  
  • Experience with high-speed protocols like PCIe/CXL.  
  • Experience in developing platform-agnostic transaction wrappers in C/C++ for protocols like PCIe/CXL/DDR.  
  • Currently based locally or open to relocation.  

The base salary range is $120,000.00 USD - $170,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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