Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Principal Design Verification Engineer - CXL/PCIe
We are seeking Principal Design Verification Engineers with extensive experience in industry-standard protocols such as PCIe and CXL. You will leverage your coding and protocol expertise to drive the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and closing coverage.
Responsibilities:
· Develop and execute block-level and system-level verification plans.
· Write and execute test sequences, collect and close coverage.
· Independently develop test plans and sequences to generate stimuli.
· Collaborate with RTL designers to debug failures.
· Develop user-controlled random constraints in transaction-based verification methodologies.
· Write assertions, cover properties, and analyze coverage data.
· Create VIP abstraction layers for sequences to simplify and scale verification deployments.
Basic Qualifications:
· Strong academic and technical background in Electrical Engineering (Bachelor’s degree required, Master’s preferred).
· Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
· Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.
· Knowledge of industry-standard simulators, revision control systems, and regression systems.
· Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.
Required Experience:
· Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
· Independent development of test plans and sequences to generate stimuli.
· Experience writing assertions, cover properties, and analyzing coverage data.
· Prior experience using Verification IPs from third-party vendors for PCIe/CXL, with exposure to Gen5 or above.
· Developing VIP abstraction layers for sequences to simplify and scale verification deployments.
· Expertise in UVM and preferred experience with DPI/C/C++ interfaces.
Preferred Experience:
· Verification expertise in Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols.
· Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
· Analyzing performance metrics of CXL/PCIe.
· System-level verification experience for PCIe/CXL.
Salary:
Your base salary will be determined based on your experience and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
