Current predictions estimate Quantum Computers (beyond current prototypes) could be available in the next 5 to 10 years. Quantum Computers are able to break or weaken most of the currently established cryptography algorithms. To still enable secure cryptography in presence of Quantum Computers new cryptography approaches, called Post-Quantum Cryptography (PQC), are heavily researched at the moment. Most of the Post-Quantum Cryptography algorithms are resource consuming. For this reason, hardware acceleration for them is urgently needed.
The Ph.D. Student (m/f/d) is expected to do research in creating efficient implementations of Post-Quantum ready cryptography algorithms. Besides implementations of cryptography algorithms, the Ph.D. student will apply a tool-based approach to explore and evaluate opportunities for hardware acceleration in the algorithms. Different options for hardware acceleration will be researched and implemented. Hardware acceleration will especially be explored for RISC-V processors. Formal methods will be used to ensure proper working and security of implemented hardware accelerations.
This work will be conducted as within a public funded research project on tool-supported efficient software/hardware implementations of cryptography algorithms on RISC-V processors.
The student's tasks include:
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