Role: Mixed Signal Verification Engineer
Location: Sunnyvale, California
Interview Process: Phone/Video
Employment Type: Contract
Mixed signal Design Verification requirements:
1. Fluent in system verilog real number modeling
2. Familiarity with writing regression tests for analog behavioral model verification
3. Familiarity with generating randomized vectors for analog behavioral model verification
4. Familiar with developing checker & writing assertions.
5. Good communication skills
6. Good debug skills
7. Experienced with gate level parasitic annotated simulations.
8. Available to work during the US work hours.
9. Hands on experience with UVM
System Verilog real number modeling
Writing regression tests for analog behavioral model verification
Generating randomized vectors for analog behavioral model verification
Developing checker & writing assertions.
1. Fluent in system verilog real number modeling
2. Familiarity with writing regression tests for analog behavioral model verification
9. Hands on experience with UVM
3. Familiarity with generating randomized vectors for analog behavioral model verification
4. Familiar with developing checker & writing assertions.
5. Good communication skills
6. Good debug skills
7. Experienced with gate level parasitic annotated simulations.
This is running mixed signal - DMS simulations and developing system verilog and EEnet based analog models
All your information will be kept confidential according to EEO guidelines.
