Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As a memory subsystem architect, you will be responsible for the memory subsystem architecture specification and its performance, power, area requirements. You will be working with the internal SW (eg. OS, Kernel, FW), System (eg. Board, Package, Power, Security), Silicon (eg. RTL, DV, PD, Perf, DFT) team members and industry consortiums such as JEDEC.
Requirements
- Knowledge in one or more of the following areas, memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory.
- Knowledge and experience with common performance benchmarks and workloads.
- Knowledge in fabric interconnect protocols such as ARM AXI and CHI.
- Ability to work well in a team and be productive under aggressive schedules.
- To work collaboratively. Excellent communication, influence, and interpersonal skills.
- Proficiency in System Verilog, C or C++, scripting languages such as Python.
- Experience with high-level simulators for performance or power estimation is a plus.
- Experience with server-class memory systems including reliability requirements and ECC algorithms is a plus.
- Experience in working with memory vendors and understanding the practical constraints on capacity/bandwidth/power is a plus.
Responsibilities
- Responsible for specifying the memory subsystem requirements (eg. PPA, RAS, QoS, Security, Debug).
- Participate and contribute in industry standard work groups (eg. JEDEC, CXL, UCIe).
- To work with the external memory and IP vendors on the technical aspects of memory products.
- Participate and contribute in micro-architecture spec of low latency and high bandwidth memory and cache controllers.
- Perform technical investigations (eg. DV/Perf) in pre-silicon simulation and post-silicon validation
Minimum Education & Experience
- Bachelor’s degree plus 5 years of industry experience.
- Master’s degree plus 3 years of industry experience.
- Ph.D with internship experience.
