Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller and Logic Design experts to join our team in building the best high performance memory interface in the world.
Responsibilities
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Validation - support test bench development and simulation for functional and performance verification
Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
Requirements
Thorough knowledge of memory controller or PHY design and experience in one or more of the following memory technologies: DDR, LPDDR, HBM
Knowledge of SystemVerilog
Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Understanding of low power microarchitecture techniques
Understanding of high performance techniques and trade-offs in memory controller microarchitecture
Experience using an interpretive language such as Perl or Python
Education and Experience
PhD, Master’s Degree, or Bachelor’s Degree in technical subject area
