Run benchmarks or key customer workloads under simulation to identify performance bottlenecks
and optimize them. Collaborate cross- functionally with Silicon design, architecture experts, and other teams across the company. Work with the silicon team to craft specifications for the future product chips and build software to run on the chips and boards. Create and maintain CI for the existing repos used by the software and the hardware team. Work closely with architecture and RTL designers on verifying the functionality correctness of the design. Develop frameworks, projects and/or tests in assembly, C/C++, SystemVerilog, or vectors according to test plans. Handling schedules and supporting multi-functional engineering effort. Assisting in verification flows, automation scripts and regressions.
Education:
- Bachelor’s or foreign equivalent in Computer Engineering, Electrical Engineering, or related field
Experience:
- 1 year of experience in job offered or related occupation
Special Requirements: Must have at least 1 year of prior work experience in each of the following:
- Analyzing and debugging Instruction Memory Access Ordering for TSO and RVWMO in RISC-V.
- Developing a pipelined RISCV based microprocessor using System Verilog that implements the
RV32I instruction.
- Creating and utilizing caches, prefetchers, and branch predictors in order to increase the hardware
- performance.
- Developing within the Linux Kernel.
- Implementing algorithms using openMP and MPI for parallel programming.
- Developing software drivers and SystemVerilog designs for high band-width buses and ports via
- FPGA and NIOS2.
- Developing a Predictive State Recurrent Neural Networks and demonstrating Predictive State
- Representation and two-stage regression.
- **Telecommuting allowed for this position**
Worksite: 3315 Scott Blvd., Floor 4, Santa Clara, CA 95054
Applicant Instructions: Include job code 91352 in reply. EOE.
