Front End ASIC Validation Engineer

You'll be part of the ASIC Front End Validation team located in Omer site. In this role you'll be responsible for: 

• Test plan definition
• FE FW driver and FE tests development in C
• DDR tests development in System Verilog
• DDR Validation tests debug in simulation and HW 
• Python scripts development

• Bs.c in Electrical or Computer Engineering - Must
• 0-2 Years of experience in validation - Must
• C coding
• Basic System Verilog and Python
• Good verbal skills
• Excellent team player skills
• Self-learning skills

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