We are looking for a Digital Design Verification Engineer to work on verification of FPGA based acceleration platform for low latency algorithmic trading. The engineer will closely engage with the FPGA design team at AlphaGrep and will be responsible for development of verification strategy, testbench and debug of FPGA based accelerators.
Primary Purpose of this Position
Unit, system and board level functional and performance verification of FPGA based accelerators and their sub modules using UVM and FPGA debug tools
Main Duties of this Position
- Planning and strategy development for thorough verification of design units and complete FPGA system
- Undertake specification capture, refinement and documentation for legacy and planned designs.
- Ownership of test-plan documentation, review and implementation using best in class practices
- Authoring of crisp supporting documentation for various stages of verification including but not limited to bug-reports, coverage closure and sign off documentation.
- Build robust, reusable test-benches from ground up using UVM with due attention to portability and coverage goals.
- Development of SystemVerilog models to capture exact design intent both in terms of performance and functionality.
- Verifying key functionalities of the design on FPGA, prior to deployment.
- Provide progress/technical updates to the project manager
- Provide project schedule estimates and technical risk identification
- Contribute to peer design reviews
- Ensure that all business activity is conducted in line with company values, policies and ethics codes of conduct.
- Undertake any other activity as reasonably requested by management
Knowledge, Skills & Experience:
Essential
- Degree qualified in electronics/ engineering related subject (preferably at 2.1 hons or higher); however, experience will be considered in lieu of formal academic qualifications
- At least 2 years of experience in Design Verification using UVM, preferably in the communications industry
- Excellent analytical and debug skills. Candidates must use their imagination to create stimulus, functional checkers, performance checkers and cover-points to stress-verify the design.
- An appreciation of digital hardware design
- Experience in developing self-contained UVM based testbenches and BFMs
- Documentation: Requirements, interface specification, test specifications
Highly desirable
- An appreciation of other engineering disciplines; Software, processor architecture and digital design in general
- Familiarity with digital communications protocols and general networking experience
- Experience of debugging FPGAs using Integrated Logic Analyzer
- Working knowledge of the following engineering tools; QuestaSim or similar, Xilinx ISE/EDK, C/C++, Soc Level Verification
- Scripting; tcl, perl
Special Features of this position:
- Ability to work individually and in a team
- Innovative thinker and problem solver
- Ability to effectively research and solve complex technical issues
- Possession of excellent interpersonal skills
Behaviours:
- Strong team player
- Good attention to detail.
- Respectful to others
- Good communication skills
- Good problem solving skills
- Proactive self-starter
- Structured and organized
- Flexible and adaptable
Location:
Mumbai, Bangalore
