FPGA Engineer - Video

Reporting to the Manager of FPGA – Imaging, this engineer will play a role in delivering best-in-class image/video processing solutions for our da Vinci systems, as part of a strong cross-functional team. The engineer in this position will work with the broader Vision and EE teams to architect, implement and verify image sensor interfaces and image processing algorithms on FPGAs deployed on the platform. This includes components in the entire processing chain, photon-to-photon: from image sensor data acquisition to stereo (and mono) displays.

The ideal candidate will possess a strong background in FPGA-based video/image processing with exposure to typical image processing algorithms and image sensor interfaces – implementation and evaluation with the trade-offs between visual quality, performance, and FPGA resource utilization in mind.

Responsibilities

• Play a role in definition and FPGA implementations of high-performance image/video processing pipelines
• Collaborate with other experts in imaging to craft the best trade-offs in resources, cost, performance, and practicality to create optimal video processing architectures
• Work with other contributors in the FPGA space to harmonize the video processing implementation with established best practices
• Work with the EE team to define image/video sensor, processing and display interfaces
• Implement designs using (System)Verilog and C/C++ (High Level Synthesis)
• Verify implemented designs in simulation and on hardware
• Collaborate on improvements to FPGA design and verification methodology; investigate new technologies that would reduce development / verification time

Required Skills

• 3+ years of experience with FPGA design implementation and verification
• Experience with SystemVerilog, C (or C++) and a scripting language such as Python or Tcl
• Experience with Vitis HLS or other high-level synthesis tools
• Understanding of and experience with high-speed digital design and associated challenges
• Foundation in using FPGA build tools such as: AMD/Xilinx, Intel and/or Lattice
• Foundation in using FPGA simulation tools, environments and in test bench development
• Understanding of static timing analysis / timing constraints; experience with timing closure
• Familiar with common image processing techniques
• Experience with revision control software e.g. Git
• Willingness to learn new skills and embrace emerging technologies

Desired Skills

• Experience with standard bus protocols e.g. AXI4 Streaming, AXI4 Memory Mapped, AXI4-Lite
• Ability to grasp complex image processing algorithms and map them to FPGA-efficient implementations

Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19.  Details can vary by role.

Intuitive is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.

Preference will be given to qualified candidates who do not reside, or plan to reside, in Alabama, Arkansas, Delaware, Florida, Indiana, Iowa, Louisiana, Maryland, Mississippi, Missouri, Oklahoma, Pennsylvania, South Carolina, or Tennessee.

We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits, and equity. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including experience, skills, and qualifications. The target salary ranges are listed.