Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a Hardware Design Engineer at Arteris, you will be involved in the development of next generation of Arteris IP solutions, enabling the creation of extremely configurable digital circuits.
The candidate will be responsible to architect and design the next generation of Arteris interconnect and system IPs for on chip and inter die communications, within best-in class area, power, performance and safety requirements.
We intend to revolutionize the way to design SoC, and we are looking for engineering talents willing to expose themselves to new design methodologies and ready to grow their skills towards both hardware and software-based development.
The position will be ideally staffed in Sophia Antipolis, France, as part of the advanced engineering team.
You will join a proven-successful company and be able to shape the future of System on Chip design.
Key Responsibilities:
Design the new elements of the next generation NoC (Switch, Sockets, protocol, transport, …) and build a best-in class communication systems for coherent & non-coherent -protocols
Contribute to the verification methodology and regression environment
Communicate with Software and Documentation teams to ensure product cohesion and overall performances
Maintain and enhance the design development flow methodology to increase automation
Experience Requirements / Qualifications:
Required:
2-3+ years of experience in HW SoC design
Proficient with HW description language (Verilog, System Verilog)
Skilled in programming languages (C++, Kotlin or Scala)
Knowledge of bus protocol architectures (AMBA)
Excellent problem solving,
Strong communication and teamwork skills,
Self-driven, able to work with minimum supervision.
Desired:
Experience with digital HW generation and Hardware construction languages
Knowledge of interconnect technology and cache coherent system
Education Requirements:
PhD or master’s degree in Computer Sciences or related field.
