Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking CPU power management experts to join our team in building the best RISC-V CPUs in the world. Responsibilities

Develop microarchitecture specifications for power management and debug features

Own RTL development of power management and debug features 

Work with verification, physical implementation, DFT and firmware teams to deliver a design which meets functional, performance, power and requirements

Work with external IP vendors to evaluate and integrate IP into the design

Use domain knowledge to propose and evaluate new features

Requirements

Knowledge of modern OoO CPU microarchitectures

2+ years of relevant industry experience in CPU power management

Knowledge of synchronous and asynchronous reset flows

Knowledge or experience with active and idle power management techniques

Proficient in SystemVerilog

Knowledge of coherent memory and bus protocols (AMBA, APB, SPI, I2C, etc.) is a plus but not required

Knowledge of RISC-V ISA is a plus but not required