CPU Design Engineer

Welcome to Codasip

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

Our processor cores are based on the RISC-V open architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.

Founded in 2014, we've grown into a thriving and talented global community. Our IP engineering teams work from offices spread across Europe, including our first and largest design center in the beautiful city of Brno, Czechia. Across Europe, we already have design teams in Cambridge, Bristol, Munich, Villeneuve-Loubet, Barcelona, Thessaloniki, Heraklion and Athens. The Codasip team is also based close to its customers, which means we have dedicated sales and application engineers in the USA, Japan, Korea, and China.

Codasip is a private company backed by well-funded EU grants. Our products are already making a real impact, with billions of devices already in the market powered by our processor IP and tools.

• Department: Labs
• Employment: Full-time
• Experience level: Mid-Senior (Ph.D./ MSc)
• Location of work is Czech Republic, preferably Brno.

YOUR MAIN RESPONSIBILITIES:

• Innovate, develop, integrate, and evaluate state-of-the-art (micro-)architectural IP cores in Codasip Studio (primarily written in Codasip Studio’s processor high-level description language, CodAL) for the next generation of Processors and Accelerators based on the RISC-V architecture.
• Customize and enhance existing Codasip RISC-V IP cores to satisfy partners'/ customers' requirements
• Participate on the the design verification and FPGA-based demonstrators.
• Participate in Codasip’s contribution to joint proof-of-concept demos with academic/ industrial partners.
• Report the technical results at international venues (e.g., RISC-V summit).

Requirements

• Recent and relevant hands-on experience with IP/Processor development.
• Background in Digital Design, computer architecture, and embedded systems.
• Experience with ASIC, FPGA design and IP verification (e.g., UVM).
• Experience in HLS (e.g., C++/Matlab/SystemC) is needed.
• Experience with VHDL/Verilog, SystemVerilog.
• SW skills: C/ C++/ Assembly, HLS, and scripting languages (bash, Python).
• Fluent written and spoken English is essential.
• Excellent communication skills, pragmatic, proactive, self-motivated, team player.

Benefits

Want to be an architect of ambition? Join Codasip

At Codasip we are committed to fostering a creative and collaborative work environment. Codasippers have the freedom to explore original ideas and experiment with new techniques. We believe in the benefits of cross-departmental collaboration and encourage sharing to build awareness throughout the teams. This enables you to add value through variety in your work.

When you join Codasip, you become part of a motivated team of self-starters where your ideas are appreciated and your voice is heard. We strive to create an environment where your ambition can flourish and your career can reach new heights. So, come and join our team of architects of ambition. We can't wait to see what you'll achieve at Codasip.

SOME USEFUL LINKS ON CODASIP:

• Codasip RISC V Processor Solutions
• Design for differentiation: architecture licenses in RISC‑V
• Scaling is Failing - Dr. Ron Black, CEO, Codasip
• Codasip Labs to accelerate advanced technologies

We're passionate about RISC-V processors and are in tune with the times! If you are, apply now :)